A UVM-based AES IP Verification Platform with Automatic Testcases Generation
نویسندگان
چکیده
ABSTRACT:This paper applied UVM (Universal Verification Methodology), an advanced verification methodology which was based on SystemVerilog language to build AES (Advanced Encryption Standard) IP verification platform and environment. Functional verification of the AES module, through a large number of testcases and constrained random test could achieve 100% functional coverage. In addition, the testcases will be run by the verification platform with automatic generation. It both can run the specified testcases in the terminal, which can customize the testcases variables through the orientation test method, and can automatically run all the testcases of the verification platform. This method could improve the efficiency and reusability of the verification, and the simulation results show that the AES IP design is successful.
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